Efforts to grow high quality, largely defect-free epitaxial layers of III-V semiconductors have been ongoing for several decades. During most of this period the use of silicon homoepitaxy, a straightforward process, has satisfied most of the commercial needs of the semiconductor technology. However, with the rapid growth of the photonics industry, and the increasingly sophisticated materials systems required for that technology, there is new impetus for the development of more effective processes for making heteroepitaxial layers in photonic materials. One of the prevalent heteroepitaxial combinations in current photonics technology is GaAs on InP. InP is a preferred substrate material because its physical properties, e.g. lattice characteristics, are reasonably dose to the active layers of interest (GaAs and GaAs ternary and quaternary materials), and it is semi-insulating. The latter property is useful for optoelectric integrated circuits (OEICs).
A variety of devices can be fabricated using this heteroepitaxial combination including lasers, modulators, and MESFET and HEMT transistors. III-V transistors may be used in purely electrical devices but are typically integrated with photonic devices as drivers for lasers etc., making the overall IC functionally photonic.
The use of InP itself as both a substrate and active semiconductor layer is convenient and eliminates the need to resort to heteroepitaxial methods. Laser-MODFET devices on InP have been reported by Y. H. Lo et al, "Multigigabit/s 1.5 .mu.m .lambda./4-shifted DFB OEIC transmitter", IEEE Photonics Tech. Lett., 1990, 2, (9), pp. 673-675. Laser-MISFET devices on InP have been reported by G. Post et al, "10 Gbit/s operations of integrated BRS laser-MISFET on indium phosphide", Microelectr. Eng., 1992, 19, pp.219-222. While these devices are useful, GaAs is a more effective material for transistor devices, and for long wavelength infra-red optical devices. Thus the ideal OEIC device uses GaAs and GaAs based semiconductor materials in the active layers, and InP as the substrate.
Techniques used to produce GaAs/InP structures are typically metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). GaAs/InP MESFET devices made by MOCVD have been reported by F. Ren et al,. "Performance of GaAs MESFETs on InP substrates", IEEE Electr. Dev. Lett., 1898, 10, pp. 389-390. Similar devices produced by MBE have been reported by Y. H. Lo et al, "High speed GaAs on InP long wavelength transmitter OEICs", Electron. Lett., 1989, 25, (10), pp. 666-667. O. Calliger et al also describe GaAs/InP heteroepitaxial techniques for OEIC devices in 8 Gbit/s GaAs-on-InP 1.3 .mu.m wavelength OEIC transmitter, IEEE Proc.-Optoelectron., 142, (1), Feb. 1995, pp. 13-16.
The heteroepitaxial process described by Calliger et al is typical of the prior art processes. Due to the significant (.about.5%) lattice mismatch between the InP substrate and the GaAs layer being deposited, the GaAs layer is highly strained and grows with large numbers of defect sites. The growth mechanism of GaAs/InP heteroepitaxy has been studied in some detail by Tanaka et al, "GaAs Heteroepitaxial Growth on an InP (001) Substrate", Japanese Journal of Applied Physics, Vol. 30, No. 9B, September 1991, pp. L 1662-L 1664. They report two dimensional (defect free) growth of GaAs for the first monolayer but, as observed by others, growth quickly deteriorates to three dimensional (strained). Defect free growth beyond 10-20 Angstroms has not been achieved reproducibly in GaAs /InP heteroepitaxial processes to date.
The effects of strained epitaxial growth in the GaAs/InP system have been partially overcome by the use of buffer layers. When GaAs growth is continued for an extended period the influence of the InP lattice decreases and eventually the dominant morphology of the grown layer reflects the properties of the GaAs lattice. At this point the GaAs layer has sufficiently few lattice defects that it is considered to be of device quality. However, to reach this state requires a buffer region of highly dislocated GaAs of the order of several microns in thickness. At typical growth rates of 0.1-1.0 monolayer (ML) per second the processing time required to produce the buffer layer is substantial and adds to the cost of the process. A process that allows the elimination of the buffer layer would be a significant advance in the technology.